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📶 Topic 10 Boolean logic · 10.1 · 10.2 · 10.3 · 10.4 · 10.5 · 10.6 · 10.7

10.1–10.7 Gates Lab

The six logic gates. NOT · AND · OR · NAND · NOR · XOR. Every symbol, every truth table, every expression. The mechanics before the composition.

🧪 Exam Mode ON — recall from memory, then reveal
§1 · Topic Overview

Where Lab A sits

Every digital device you own runs on electricity at one voltage. But binary needs two states — 0 and 1. Logic gates are the tiny switches that translate one into the other. They are the atoms of computation.

In this lab you'll meet the six standard logic gates of the Cambridge 0478 syllabus: NOT · AND · OR · NAND · NOR · XOR. For each one you'll learn the symbol, the behaviour, the truth table, and how to write it as a logic expression.

This is the mechanics lab. Lab B composes gates into circuits. Lab C applies circuits to real-world problems. But none of that works until the six gates are cold.

📶 The Signal metaphor

"The gate fires. The signal responds." Each gate is a switch. You put signals in. You get a signal out. Every gate has its own rule for which combinations of inputs turn the output high.

§2 · Learning Objectives

By the end of Lab A you will be able to:

  • Draw the standard Cambridge symbol for each of the six gates (NOT, AND, OR, NAND, NOR, XOR) from memory
  • Name any gate shown as a symbol
  • State the number of inputs each gate accepts (NOT = 1; all others = 2)
  • Complete a truth table for any single gate
  • Write the logic expression for any single gate — in both word form (X = A AND B) and symbolic form (X = A · B)
  • Recognise the "opposite output" relationship between AND↔NAND and OR↔NOR
§3 · Key Terminology

The nine words Cambridge expects

Wording matches the textbook exactly — Cambridge marks against textbook language.

Voltage — the pressure that forces charged electrons to flow in an electrical circuit.
Logic gate — a very small component in a computer system that controls the flow of electricity.
Boolean value — a value with only two possible states — true or false, or in a logic gate's case 0 or 1.
Input — a value going into a gate (labelled A, or A and B).
Output — the value produced by a gate (labelled X).
Truth table — a method to show all the different combinations that can be used as input values and what the output value will be for those input values.
Logic expression — a mathematical representation that is used to represent an electrical circuit or system.
High voltage / low voltage — High = 1 (electricity flowing at full pressure). Low = 0 (electricity changed to low pressure).
Vinculum — the horizontal line drawn over a variable to indicate NOT (as in Ā = NOT A).
§4 · Core Theory

§4.1 · Why gates exist (the electricity story)

  1. Computers run on electricity at one set voltage.
  2. Binary needs two states (0 and 1) to represent data.
  3. To turn one voltage into two states, computers use logic gates.
  4. Each gate acts as a switch — it takes one or two inputs and produces one output at either high (1) or low (0) voltage.
  5. Modern computers use thousands of gates to process and store data.
Cambridge mark-scheme phrase: "Data is processed in a computer by using logic gates …" — 2023 P2 specimen mark scheme, Q1(b)

§4.2 · How to read a gate

Every gate has three things you need to recognise:

  1. A symbol — a specific shape drawn to Cambridge BS/ANSI convention. Cambridge marks against these exact shapes; substitutes lose marks.
  2. A behaviour — a rule about what output the gate produces for each combination of inputs.
  3. A logic expression — a mathematical shorthand for the behaviour, in one of two forms:
    • Word form — e.g. X = A AND B
    • Symbolic form — e.g. X = A · B (dot for AND, plus for OR, overbar for NOT)

Truth tables show all four (or two, for NOT) input combinations and the output for each.

§4.3 · Number of inputs — the first thing to remember

NOT has 1 input. Only one. Ever.

All other gates (AND, OR, NAND, NOR, XOR) have 2 inputs.

This is question-worthy on its own. Cambridge 0478 syllabus 10.1.d asks this directly. A NOT gate drawn with two inputs = zero marks.

§4.4 · The six gates at a glance

GateInputsOutput = 1 when…Word expressionSymbolic
NOT1input is 0X = NOT AX = Ā
AND2both inputs are 1X = A AND BX = A · B
OR2either or both inputs are 1X = A OR BX = A + B
NAND2either input is 0 (or both)X = A NAND BX = A·B (overbar over both)
NOR2both inputs are 0X = A NOR BX = A+B (overbar over both)
XOR2exactly one input is 1X = A XOR BX = A ⊕ B

🎯 Pattern spotting

  • NAND is the opposite of AND — every row of the output column flipped.
  • NOR is the opposite of OR — every row of the output column flipped.
  • XOR is like OR except when both inputs are 1, then it's 0.
§5 · Worked Examples · one per gate

The six gates, one by one — the doorway-guard tour

Each gate as a doorway guard. Different guards, different rules. The metaphor is from the textbook and it holds — remember the guard's rule, remember the gate.

§6 · Common Misconceptions · 10 traps

Where students lose marks (and how not to)

Five traps come from Cambridge Principal Examiner Reports; five come from the textbook and syllabus. Every one has a fix.

§7 · Cambridge Exam Focus

Mark-scheme language — memorise these phrases

These phrases appear verbatim on Cambridge Paper 2 (Algorithms, Programming and Logic) — P21/P22/P23 under the 2023-onwards syllabus. Using them in answers earns marks.

"has two inputs and one output" — the standard opening for every gate except NOT
"has one input and one output" — used for NOT gate only
"the output is 1 when …" — Cambridge stem for gate-behaviour questions
"the standard symbol for a NOR gate" — 2025 examiner language when symbol correctness matters
"as shown in the syllabus" — Cambridge phrasing when the exact BS/ANSI symbol is required
"a solid-state drive uses NAND gates" — real-world context (F/M26 P22 style)
"contains logic gates/switches" — 2023 specimen MS Q1(b) mark point
"process the values 1 and 0" — 2024 mark point wording
"that only have two states" — 2024 mark point wording
§8 · Quick Knowledge Check

Six memory-recall questions — tap to reveal

0 / 6 revealed

Q1 · How many inputs does a NOT gate have?
1. Only NOT has 1 input. All other Cambridge gates (AND, OR, NAND, NOR, XOR) have 2.
Q2 · How many inputs does an AND gate have?
2. Every gate except NOT has 2 inputs — A and B.
Q3 · What is the output of an AND gate when both inputs are 1?
1. AND outputs 1 only when both inputs are 1. It's the "both must be true" gate.
Q4 · What is the output of a NAND gate when both inputs are 1?
0. NAND is the opposite of AND. If AND gives 1, NAND gives 0.
Q5 · What is the output of an XOR gate when both inputs are 1?
0. XOR means Exclusive OR — one or the other, but not both. Both = 1 gives 0. (This is the classic XOR-vs-OR trap.)
Q6 · What symbol represents OR in the alternative notation?
+ (plus). Dot (·) for AND — "both multiplied together". Plus (+) for OR — "either added together works". Overbar for NOT.
§9 · Ready for the next lab?

✅ You know the six gates — cold.

You can draw the symbol, complete the truth table, and write the logic expression for any single gate in isolation.

Next up: Lab B · Circuit (Composition) — where you'll wire these gates together into circuits, convert between expressions, truth tables, and circuits, and start reading the multi-gate questions Cambridge tests every year.

📊 Where you are

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🎯 Weakest gates

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📶 The Signal arc

Topic 10 · Lab A teaches gate mechanics. Then Lab B composes gates into circuits. Then Lab C applies circuits to real-world problems.

The gate fires. The signal responds.

🎓 The gates, explained

The Learn tab takes the six gates and slows them down. Each one gets a diagram, an explanation, and a walk-through of its behaviour. When you're done here, head to Activities and open the Gate Trainer.

The anatomy of a gate

Every Cambridge gate symbol has three parts you draw:

1 · Input lines — one for NOT, two for all other gates. Labelled A (and B, for 2-input gates).

2 · The body — the shape of the gate. AND has a flat back and a D-shaped front. OR has a concave back and a pointed front. NOT is a triangle.

3 · The output line — labelled X. If the gate is a "NOT-something" (NAND, NOR, or NOT itself), there's a small bubble at the output tip.

🔍 Contrast box · NAND vs AND

The difference between AND and NAND is one small circle. That circle inverts every output.

AND

Output = 1 when both inputs are 1.

ABX
000
010
100
111
NAND

Output = flipped AND. Both 1s gives 0; anything else gives 1.

ABX
001
011
101
110

The rule: every N-gate (NAND, NOR, NOT) has an output bubble. No bubble, no inversion, no marks. This is Trap 5 from the Review tab.

The six gates side by side

Same layout for every gate. Symbol · rule · truth table · expression. This is exactly what you'll see on the Cambridge paper.

Reading a truth table — the Cambridge order

2-input truth tables always show the same four rows, always in the same order:

ABX
00?
01?
10?
11?

Read down A first, then B. A = 0, B = 0. A = 0, B = 1. A = 1, B = 0. A = 1, B = 1. Every gate you'll ever meet uses this order. Miss a row (or put them in a weird order) and you drop marks.

🧠 Row count rule

2 inputs → 4 rows. 1 input (NOT) → 2 rows. Both students and examiners take a full mark off for skipped rows.

Ready for Activities?

The Gate Trainer has 4 modes. Symbol → Name (easiest) walks up to Sprint (hardest). Start on Mode 1 and let the adaptive weighting surface the gates you're weakest on.

🎯 Cambridge exam anchors

Lab A drills these Cambridge Paper 2 skills:

  • 10.1.b — Recognise the six standard gates
  • 10.1.c — Draw the correct symbol (BS/ANSI)
  • 10.1.d — State the number of inputs each gate takes
  • 10.2.a — Complete a truth table for a single logic gate

Not in this lab (Lab B / Lab C territory): multi-gate circuits, expression↔circuit conversion, problem-statement questions.

🎮 Gate Trainer

Four modes. Each one drills a different Cambridge exam skill. Adaptive weighting means the gates you get wrong come back more often (2× likelihood); the gates you master fade to the background (0.2×).

Sprint is 60 seconds of mixed drills — but it stays locked until you've attempted Modes 1, 2, and 3 at least once. No skipping the fundamentals.

60-second Sprint

Mixed drills from Modes 1–3. Adaptive: weak gates surface 2× more often. Streaks show at 5 · 10 · 15 correct.

60Seconds left
0Correct
0Streak

📶 Gate coverage

One drill per gate at minimum. Weak gates surface more often.

💡 Mode guide

Mode 1 · Symbol → Name. See the SVG, name the gate. Trains Cambridge P22 Q2-style symbol-recognition.

Mode 2 · Name → Truth Table. See "XOR", fill in the 4 output cells in Cambridge order. Trains 10.2.a.

Mode 3 · Inputs → Output. See gate + specific A/B, predict X. Trains gate-behaviour recall.

Mode 4 · Sprint. 60s mixed drill for exam speed.

✎ Practice — 18 adaptive MCQs

Weighting adapts to your accuracy: weak gates come back 2× as often, mastered gates fade to 0.2×. Filter by difficulty or run the whole pool. Missed questions log automatically to Mistakes.

🧪 Practice Exam Mode ON. No multiple-choice options shown — recall the answer, then reveal and self-mark.

📊 Practice stats

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📋 Exam pool — 12 past-paper questions

Every question traces to a real Cambridge Paper 2 (Algorithms, Programming and Logic — P21/P22/P23 under the 2023-onwards syllabus) or earlier Paper 1 for pre-syllabus material. Write your answer, then self-mark against the mark scheme.

📋 Exam stats

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ℹ️ About the citations

Topic 10 lives on Paper 2 under the 2023-onwards 0478 syllabus (Algorithms, Programming and Logic). 2022 items reference Paper 1 because that was pre-syllabus-change. E12 is a synthetic exam-style composite.

🔄 Review — the 10 traps + memory triggers

Cambridge Principal Examiner Reports call out the same mistakes every year. Read these before your exam. Then look at Mistakes to see the ones you keep making.

Examiner-cited & source-cited trap cards

🧠 Memory triggers

Six one-liners. If you can recite these before your exam, you know the six gates.

🎯 Your weakest gates

💔 Your logged mistakes

🏆 Mastery — 12-item revision checklist

Tick each item as you master it. Tap any status chip to manually override (respects student autonomy — per Master Prompt Pack). When all 12 are ticked, the Module Mastered banner unlocks.

🏆 Module Mastered — Topic 10 · Lab A · Signal complete!

Revision checklist

Skill grid — per-gate mastery

Mastered = 3+ attempts and ≥70% accuracy. Tap the status chip to manually override.

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💔 Mistakes

Your mistakes log

Every wrong Practice/Exam answer captures here automatically. Review before your next attempt.

📊 Progress

Progress dashboard

Your attempts, accuracy, and mastery counts across Lab A.

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🎯 Weakest gates

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