3.1 CPU & Von Neumann Trainer
Master the CPU architecture — registers, buses, ALU and Control Unit. The foundation for the rest of Topic 3.
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What do I need to know before I start?
The CPU is the part of the computer that runs the Fetch–Decode–Execute (FDE) cycle. Calling it "the brain of the computer" scores zero in the exam — Cambridge wants "runs the FDE cycle" or "processes and executes instructions". For 3.1 you need the Von Neumann architecture, the roles of the ALU and Control Unit, and the five named registers and exactly what each one holds.
By the end of 3.1 you can…
| Objective | Why it matters |
|---|---|
| State the purpose of the CPU precisely | s25 examiner report: "brain of the computer" scores 0. Say "runs the FDE cycle" / "processes and executes instructions". |
| Describe the Von Neumann architecture | Data and instructions share the same memory and the same buses — a defining exam point. |
| Describe the three stages of the FDE cycle | Appears regularly — fetch from memory, decode by the CU, execute by the CPU/ALU. |
| Name and describe all five registers — PC, MAR, MDR, ACC, CIR | m24 — 5-mark register table. s25 — identify three registers used in the fetch stage. |
| Correct the common register misconceptions | m24 mark scheme: MAR stores addresses NOT instructions; MDR stores data from the bus NOT from the PC. |
| Describe the three buses | Address bus (unidirectional), data bus (bidirectional), control bus (carries signals). |
Cambridge-approved terms
Central Processing Unit. Runs the Fetch–Decode–Execute cycle. Contains the ALU, Control Unit, registers and cache.
Arithmetic Logic Unit. Performs arithmetic (add, subtract) and logical comparisons.
Manages the flow of data and instructions inside the CPU. Coordinates the FDE cycle and decodes instructions.
An architecture where data and instructions are stored in the same memory and share the same buses.
A small, very fast storage location inside the CPU that holds one piece of data or one instruction during processing.
A set of parallel wires that carries data, addresses or control signals between the CPU and memory.
The tables you must know cold
1. The Fetch–Decode–Execute cycle
| Stage | What happens | Who does it |
|---|---|---|
| Fetch | The next instruction is fetched from memory. The address in the PC is copied to the MAR and sent along the address bus; the PC is incremented by 1; the instruction is sent along the data bus into the MDR, then copied into the CIR. | PC → MAR → MDR → CIR |
| Decode | The Control Unit decodes the instruction — working out what operation is needed and what data is required. | Control Unit |
| Execute | The instruction is carried out. If arithmetic or logic is needed the ALU is used; the result may be stored in the ACC. | ALU / CPU |
2. The five registers — Cambridge definitions
| Register | Full name | Cambridge definition |
|---|---|---|
| PC | Program Counter | Stores the address of the next instruction to be fetched from memory. It is incremented during each fetch. |
| MAR | Memory Address Register | Stores the address of the memory location being accessed — NOT instructions. |
| MDR | Memory Data Register | Stores the data or instruction fetched from memory, or waiting to be written to memory. It arrives via the data bus — NOT from the PC. |
| ACC | Accumulator | Stores the result of interim calculations performed by the ALU. |
| CIR | Current Instruction Register | Stores the instruction currently being decoded/executed. |
3. The three buses
| Bus | Direction | Carries |
|---|---|---|
| Address bus | Unidirectional (CPU → memory) | The address of the memory location to read from or write to. |
| Data bus | Bidirectional | The data or instruction being transferred between CPU and memory. |
| Control bus | Bidirectional | Control and timing signals sent by the Control Unit. |
Traps that regularly cost marks
s25 examiner report: this scores 0 for purpose. Say "runs the FDE cycle" or "processes and executes instructions".
m24 mark scheme: the MAR stores addresses. The CIR stores the instruction. Confusing MAR and CIR is the most common register error.
m24 mark scheme: the MDR stores data passed from the bus. The PC only holds the address of the next instruction.
The PC holds the address of the next instruction; the CIR holds the current instruction being processed.
The defining feature is that data and instructions share the same memory and buses — not separate ones.
The address bus is unidirectional (CPU → memory). The data and control buses are bidirectional.
Check yourself — tap to reveal
Answer in your head, then tap to see the model answer. Aim for 5 of 6 before moving to Learn.
✅ Ready for Learn?
Before moving on, make sure you can answer these without notes:
- What is the purpose of the CPU? (Cambridge-approved phrasing only.)
- What are the three stages of the FDE cycle and what happens in each?
- What does each of PC, MAR, MDR, ACC and CIR store?
- What defines the Von Neumann architecture?
- Which bus is unidirectional, and why?
What is the CPU?
Processes data and instructions
The Central Processing Unit processes data and instructions by running the Fetch–Decode–Execute cycle. Every action a computer takes — opening a file, displaying a letter, calculating a sum — is processed by the CPU.
Von Neumann architecture
In a Von Neumann system, data and instructions are stored in the same memory (RAM). They share the same buses. This is the architecture Cambridge tests.
FDE cycle in action
Watch the Fetch-Decode-Execute cycle step through, or control each stage manually.
Memory
CPU
Result
Press a button to step through the FDE cycle.
Inside the CPU — two main units
ALU (Arithmetic Logic Unit)
Performs all mathematical calculations (add, subtract, multiply) and logical comparisons (AND, OR, greater than, equal to). Uses the ACC (accumulator) to store interim results.
CU (Control Unit)
Controls and coordinates all operations in the CPU. Decodes instructions using the instruction set. Sends timing signals to components via the control bus.
Five registers you MUST know
| Register | Full name | Purpose |
|---|---|---|
| PC | Program Counter | Stores the address of the NEXT instruction to be fetched |
| MAR | Memory Address Register | Stores the address of data/instruction to be read from or written to RAM |
| MDR | Memory Data Register | Stores the data/instruction fetched from or sent to RAM |
| CIR | Current Instruction Register | Stores the current instruction being decoded/executed |
| ACC | Accumulator | Stores interim calculation results from the ALU |
Three buses
Address bus
Carries addresses between CPU and memory. Unidirectional (CPU → memory only).
Data bus
Carries data/instructions between CPU and memory. Bidirectional (both ways).
Control bus
Carries control and timing signals (e.g. read/write) between the CU and other components. Bidirectional.
Quick check
The MAR stores:
Activity 1 — Name the Component
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Activity 2 — Register Matcher
Which register does this describe?
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Activity 3 — Spot the Mistake
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Practice questions
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Cambridge-style questions
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Review quiz
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Exam traps
Memory triggers
🧠 "MAR = Memory Address, MDR = Memory Data"
The clue is in the name. Address register holds addresses. Data register holds data.
🧠 "ALU = Arithmetic, CU = Control"
A = arithmetic. C = control. They never swap roles.
🧠 "PC points to the NEXT instruction"
Not the current one — that's the CIR. PC always looks ahead.