3.2 Fetch-Decode-Execute Lab
Step through the FDE cycle at register level — the 5-mark question Cambridge asks every session.
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What do I need to know before I start?
The Fetch–Decode–Execute (FDE) cycle is how the CPU processes every instruction, one at a time. It has three stages: Fetch gets the next instruction from memory, Decode works out what it means, and Execute carries it out. Cambridge tests this with diagram questions, "put the steps in order" questions, and "identify the registers/buses used" questions — all needing exact vocabulary. Master the sequence and the role of each register, bus and component at every stage.
By the end of 3.2 you can…
| Objective | Why it matters |
|---|---|
| State the steps of the fetch stage in the correct order | s24 — 4-mark diagram question; any four correct steps from the sequence earn marks. |
| Name the three registers and two buses used in fetch | s25 — registers: PC, MAR, MDR (CIR accepted); buses: address and data. |
| State that the PC increments after sending the address to the MAR | s24 mark scheme — a specific, separately credited mark point. |
| Describe the decode stage: split into opcode and operand | s24 mark scheme (5b) — CIR/CU receives instruction → split into opcode/operand → decoded using the instruction set. |
| Define the instruction set precisely | s25 mark scheme: "a list of all the commands that can be processed by the CPU". |
| Describe the execute stage and the role of the ALU and ACC | s25 mark scheme: "ALU performs the mathematical/logical operation"; "accumulator stores the result of interim calculations". |
Cambridge-approved terms
Program Counter — holds the address of the next instruction to be fetched, then increments.
Memory Address Register — receives the address from the PC and sends it to RAM via the address bus.
Memory Data Register — receives the fetched instruction from RAM via the data bus.
Current Instruction Register — stores the instruction currently being decoded and executed.
The instruction splits into an opcode (what to do) and an operand (what to do it to).
A list of all the commands that can be processed by the CPU.
Decodes the instruction and coordinates the cycle, sending signals along the control bus.
Arithmetic Logic Unit — carries out arithmetic and logical operations during execute.
Accumulator — stores the result of interim calculations. Built into the ALU.
The three stages, step by step
Stage 1 · Fetch
| Step | What happens |
|---|---|
| 1 | The address of the next instruction is copied from the PC to the MAR. |
| 2 | The PC increments so it points to the next instruction. |
| 3 | The MAR sends the address to RAM along the address bus. |
| 4 | The Control Unit sends a read signal along the control bus. |
| 5 | The instruction is fetched from RAM and travels back along the data bus into the MDR. |
| 6 | The instruction is copied from the MDR into the CIR, ready to be decoded. |
Stage 2 · Decode
| Step | What happens |
|---|---|
| 1 | The instruction is held in the CIR. |
| 2 | The Control Unit decodes it, splitting it into an opcode (the operation) and an operand (the data or address). |
| 3 | The opcode is checked against the instruction set to work out what to do. |
Stage 3 · Execute
| Step | What happens |
|---|---|
| 1 | The CPU carries out the decoded instruction. |
| 2 | If arithmetic or logic is needed, the ALU performs it; the result is stored in the ACC. |
| 3 | Data may be read from or written to memory, or the program may jump to a new address. |
| 4 | The PC has already incremented, so the cycle repeats from fetch. |
Traps that cost marks every session
For execute, Cambridge requires "the CPU carries out the decoded instruction" — name the ALU/ACC where relevant, don't be vague.
s24 mark scheme: the PC increments after sending the address to the MAR. It's a separate mark — don't skip it.
The MDR receives the instruction from RAM via the data bus, not from the PC. The PC only holds the next address.
The opcode says what to do; the operand says what to do it to. They are two different parts of one instruction.
Define it exactly: "a list of all the commands that can be processed by the CPU".
The address bus is unidirectional (CPU → memory). The data bus is bidirectional.
Check yourself — tap to reveal
Answer in your head, then tap to see the model answer. Aim for 5 of 6 before moving to Learn.
✅ Ready for Learn?
Before moving on, make sure you can answer these without notes:
- What happens in each of the three FDE stages, in order?
- Which registers and buses are used in the fetch stage?
- When does the PC increment?
- What is the difference between opcode and operand?
- What is the role of the ALU and ACC during execute?
The three stages
1. Fetch
The next instruction is retrieved from RAM and brought into the CPU. This is where PC, MAR, MDR and CIR are all used.
2. Decode
The CU decodes the instruction in the CIR using the instruction set to work out what action is needed.
3. Execute
The instruction is carried out. If calculations are needed, the ALU is used and results go to the ACC.
Fetch stage — register by register
This is the stage that earns the most marks. Learn each micro-step.
FDE cycle animation
Watch the complete cycle at register level. Each micro-step highlights.
Press ▶ Run to watch the full FDE cycle step by step.
Decode + Execute detail
Decode
The CU receives the instruction from the CIR. It uses the instruction set (all commands the CPU understands, in machine code) to decode what the instruction means and determine what action is required.
Execute
The decoded instruction is carried out. If arithmetic or logic is needed, data is sent to the ALU. The ALU performs the operation and stores interim results in the ACC. The final result may be written back to memory via the data bus.
Quick check
During the fetch stage, what happens AFTER the instruction arrives in the MDR?
Activity 1 — Which Stage?
Press New Question.
Activity 2 — What Happens Next?
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Activity 3 — Spot the Mistake
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Adaptive practice
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Cambridge-style questions
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Review quiz
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Exam traps
Memory triggers
🧠 "PC → MAR → RAM → MDR → CIR"
The fetch flow. Five components, five potential marks. Learn this sequence by heart.
🧠 "CU = decode, ALU = execute"
The CU decodes. The ALU executes calculations. Don't mix them.
🧠 "PC always moves forward"
After fetching, PC increments to point to the NEXT instruction. The cycle never stops.